Infineon SRAM- 128 MB
- N° de stock RS:
- 273-5438
- Référence fabricant:
- S70KL1282GABHV020
- Fabricant:
- Infineon
Offre groupée disponible
Sous-total (1 unité)*
5,00 €
(TVA exclue)
6,05 €
(TVA incluse)
Frais de livraison offerts pour toute commande de plus de 75,00 €
Stock limité
- 1 unité(s) prête(s) à être expédiée(s) d'un autre centre de distribution
Besoin de plus? Cliquez sur " Vérifier les dates de livraison " pour plus de détails
Unité | Prix par unité |
|---|---|
| 1 - 9 | 5,00 € |
| 10 - 24 | 4,61 € |
| 25 - 49 | 4,43 € |
| 50 - 99 | 4,34 € |
| 100 + | 4,04 € |
*Prix donné à titre indicatif
- N° de stock RS:
- 273-5438
- Référence fabricant:
- S70KL1282GABHV020
- Fabricant:
- Infineon
Spécifications
Documentation technique
Législations et de normes
Détails du produit
Recherchez des produits similaires en sélectionnant un ou plusieurs attributs.
Sélectionner tout | Attribut | Valeur |
|---|---|---|
| Marque | Infineon | |
| Memory Size | 128MB | |
| Product Type | SRAM | |
| Number of Bits per Word | 16 | |
| Maximum Random Access Time | 35ns | |
| Maximum Clock Frequency | 200MHz | |
| Minimum Supply Voltage | 1.8V | |
| Timing Type | DDR | |
| Maximum Supply Voltage | 3V | |
| Minimum Operating Temperature | -40°C | |
| Package Type | FBGA-24 Ball | |
| Maximum Operating Temperature | 105°C | |
| Standards/Approvals | No | |
| Series | HYPERRAM | |
| Automotive Standard | AEC-Q100 | |
| Sélectionner tout | ||
|---|---|---|
Marque Infineon | ||
Memory Size 128MB | ||
Product Type SRAM | ||
Number of Bits per Word 16 | ||
Maximum Random Access Time 35ns | ||
Maximum Clock Frequency 200MHz | ||
Minimum Supply Voltage 1.8V | ||
Timing Type DDR | ||
Maximum Supply Voltage 3V | ||
Minimum Operating Temperature -40°C | ||
Package Type FBGA-24 Ball | ||
Maximum Operating Temperature 105°C | ||
Standards/Approvals No | ||
Series HYPERRAM | ||
Automotive Standard AEC-Q100 | ||
The Infineon DRAM is a high speed CMOS self refresh DRAM, with HYPERBUS™ interface. The DRAM array uses dynamic cells that require periodic refresh. Refresh control logic within the device manages the refresh operations on the DRAM array when the memory is not being actively read or written by the HYPERBUS™ interface master. Since the host is not required to manage any refresh operations, the DRAM array appears to the host as though the memory uses static cells that retain data without refresh. Hence, the memory is more accurately described as pseudo static RAM.
HYPERBUS™ interface
200 MHz maximum clock rate
Configurable burst characteristics
Data throughput up to 400 MBps
Bidirectional read write data strobe
Optional DDR centre aligned read strobe