Nexperia 74HCT165D,653 1 Surface Shift Register 74HCT SO, 16-Pin
- N° de stock RS:
- 170-8015
- Référence fabricant:
- 74HCT165D,653
- Fabricant:
- Nexperia
Sous-total (1 bobine de 2500 unités)*
615,00 €
(TVA exclue)
745,00 €
(TVA incluse)
Frais de livraison offerts pour toute commande de plus de 90,00 €
Temporairement en rupture de stock
- Expédition à partir du 27 octobre 2026
Besoin de plus? Cliquez sur " Vérifier les dates de livraison " pour plus de détails
Unité | Prix par unité | la bobine* |
|---|---|---|
| 2500 + | 0,246 € | 615,00 € |
*Prix donné à titre indicatif
- N° de stock RS:
- 170-8015
- Référence fabricant:
- 74HCT165D,653
- Fabricant:
- Nexperia
Spécifications
Documentation technique
Législations et de normes
Détails du produit
Recherchez des produits similaires en sélectionnant un ou plusieurs attributs.
Sélectionner tout | Attribut | Valeur |
|---|---|---|
| Marque | Nexperia | |
| Product Type | Shift Register | |
| Package Type | SO | |
| Logic Family | 74HCT | |
| Mount Type | Surface | |
| Number of Elements | 1 | |
| Pin Count | 16 | |
| Minimum Supply Voltage | 4.5V | |
| Maximum Supply Voltage | 5.5V | |
| Trigger Type | Positive Edge | |
| Maximum Operating Temperature | 125°C | |
| Standards/Approvals | No | |
| Length | 10mm | |
| Series | 74HCT165 | |
| Height | 1.75mm | |
| Automotive Standard | No | |
| Sélectionner tout | ||
|---|---|---|
Marque Nexperia | ||
Product Type Shift Register | ||
Package Type SO | ||
Logic Family 74HCT | ||
Mount Type Surface | ||
Number of Elements 1 | ||
Pin Count 16 | ||
Minimum Supply Voltage 4.5V | ||
Maximum Supply Voltage 5.5V | ||
Trigger Type Positive Edge | ||
Maximum Operating Temperature 125°C | ||
Standards/Approvals No | ||
Length 10mm | ||
Series 74HCT165 | ||
Height 1.75mm | ||
Automotive Standard No | ||
The 74HC165, 74HCT165 are high-speed Si-gate CMOS devices. They are pin compatible with Low-power Schottky TTL (LSTTL). The 74HC165, 74HCT165 are 8-bit parallel-load or serial-in shift registers with complementary serial outputs (Q7 and Q7) available from the last stage. When the parallel load (PL) input is LOW, parallel data from the D0 to D7 inputs are loaded into the register asynchronously. When PL is HIGH, data enters the register serially at the DS input and shifts one place to the right (Q0 → Q1 → Q2, etc.) with each positive-going clock transition. This feature allows parallel-to-serial converter expansion by tying the Q7 output to the DS input of the succeeding stage. The clock input is a gated-OR structure which allows one input to be used as an active LOW clock enable (CE) input.
Simple control interface
I/O expansion
Asynchronous and synchronous load options
High frequency
Cascadable
LED drivers
Key applications
Displays
Control units