Nexperia 74HCT4094D,118 1 Surface Shift Register 74HCT SO, 16-Pin
- N° de stock RS:
- 170-8030
- Référence fabricant:
- 74HCT4094D,118
- Fabricant:
- Nexperia
Actuellement indisponible
Nous ne savons pas si cet article sera de nouveau disponible. RS a l'intention de le retirer de son assortiment sous peu.
- N° de stock RS:
- 170-8030
- Référence fabricant:
- 74HCT4094D,118
- Fabricant:
- Nexperia
Spécifications
Documentation technique
Législations et de normes
Détails du produit
Recherchez des produits similaires en sélectionnant un ou plusieurs attributs.
Sélectionner tout | Attribut | Valeur |
|---|---|---|
| Marque | Nexperia | |
| Product Type | Shift Register | |
| Package Type | SO | |
| Logic Family | 74HCT | |
| Mount Type | Surface | |
| Number of Elements | 1 | |
| Minimum Supply Voltage | 4.5V | |
| Pin Count | 16 | |
| Maximum Supply Voltage | 5.5V | |
| Trigger Type | Positive Edge | |
| Maximum Operating Temperature | 125°C | |
| Length | 10mm | |
| Height | 1.75mm | |
| Series | 74HCT4094 | |
| Width | 4mm | |
| Standards/Approvals | No | |
| Automotive Standard | No | |
| Sélectionner tout | ||
|---|---|---|
Marque Nexperia | ||
Product Type Shift Register | ||
Package Type SO | ||
Logic Family 74HCT | ||
Mount Type Surface | ||
Number of Elements 1 | ||
Minimum Supply Voltage 4.5V | ||
Pin Count 16 | ||
Maximum Supply Voltage 5.5V | ||
Trigger Type Positive Edge | ||
Maximum Operating Temperature 125°C | ||
Length 10mm | ||
Height 1.75mm | ||
Series 74HCT4094 | ||
Width 4mm | ||
Standards/Approvals No | ||
Automotive Standard No | ||
The 74HC4094, 74HCT4094 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. The device features a serial input (D) and two serial outputs (QS1 and QS2) to enable cascading. Data is shifted on the LOW-to-HIGH transitions of the CP input. Data is available at QS1 on the LOW-to-HIGH transitions of the CP input to allow cascading when clock edges are fast. The same data is available at QS2 on the next HIGH-to-LOW transition of the CP input to allow cascading when clock edges are slow. The data in the shift register is transferred to the storage register when the STR input is HIGH. Data in the storage register appears at the outputs whenever the output enable input (OE) is HIGH.
Simple control interface
I/O expansion
Asynchronous and synchronous load options
High frequency
Cascadable
LED drivers
Key applications
Displays
Control units