Renesas Electronics 85102AGILF Clock Buffer, 16-Pin 7 TSSOP
- N° de stock RS:
- 216-6208
- Référence fabricant:
- 85102AGILF
- Fabricant:
- Renesas Electronics
Offre groupée disponible
Sous-total (1 unité)*
14,44 €
(TVA exclue)
17,47 €
(TVA incluse)
Frais de livraison offerts pour toute commande de plus de 75,00 €
Dernier stock RS
- 72 dernière(s) unité(s), prête(s) à l'envoi d'un autre centre de distribution
Unité | Prix par unité |
|---|---|
| 1 - 9 | 14,44 € |
| 10 - 24 | 13,28 € |
| 25 - 49 | 12,73 € |
| 50 - 99 | 12,24 € |
| 100 + | 11,22 € |
*Prix donné à titre indicatif
- N° de stock RS:
- 216-6208
- Référence fabricant:
- 85102AGILF
- Fabricant:
- Renesas Electronics
Spécifications
Documentation technique
Législations et de normes
Détails du produit
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Sélectionner tout | Attribut | Valeur |
|---|---|---|
| Marque | Renesas Electronics | |
| Product Type | Clock Buffer | |
| Mount Type | Surface | |
| Package Type | TSSOP | |
| Pin Count | 16 | |
| Minimum Supply Voltage | 3V | |
| Maximum Supply Voltage | 3.3V | |
| Minimum Operating Temperature | -40°C | |
| Maximum Operating Temperature | 85°C | |
| Length | 5mm | |
| Width | 4.4 mm | |
| Height | 1mm | |
| Series | 85102A | |
| Standards/Approvals | No | |
| Maximum Output Frequency | 200MHz | |
| Automotive Standard | No | |
| Number of Outputs | 7 | |
| Sélectionner tout | ||
|---|---|---|
Marque Renesas Electronics | ||
Product Type Clock Buffer | ||
Mount Type Surface | ||
Package Type TSSOP | ||
Pin Count 16 | ||
Minimum Supply Voltage 3V | ||
Maximum Supply Voltage 3.3V | ||
Minimum Operating Temperature -40°C | ||
Maximum Operating Temperature 85°C | ||
Length 5mm | ||
Width 4.4 mm | ||
Height 1mm | ||
Series 85102A | ||
Standards/Approvals No | ||
Maximum Output Frequency 200MHz | ||
Automotive Standard No | ||
Number of Outputs 7 | ||
The Renesas Electronics 85102I is a low skew, high performance 1-to-2 Differential-to-HCSL fanout buffer. The 85102I has a differential clock input. The CLK0, nCLK0 input pair can accept most standard differential input levels. The clock enable is internally synchronized to eliminate runt clock pulses on the output during asynchronous assertion/ deassertion of the clock enable pin. Guaranteed output and part-to-part skew characteristics make the 85102I ideal for those applications demanding well defi ned performance and repeatability.
Two 0.7V differential HCSL outputs
Selectable differential CLK0, nCLK0 or LVCMOS inputs
CLK0, nCLK0 pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL
CLK1 can accept the following input levels:
LVCMOS or LVTTL
Maximum output frequency: 500MHz
Translates any single-ended input signal to 3.3V
HCSL levels with resistor bias on nCLK input
Output skew: 65ps (maximum)
Part-to-part skew: 600ps (maximum)
Propagation delay: 3.2ns (maximum)