8305AGILF, Clock Buffer, 5-Input, 16-Pin TSSOP
- N° de stock RS:
- 216-6204
- Référence fabricant:
- 8305AGILF
- Fabricant:
- Renesas Electronics
Offre groupée disponible
Sous-total (1 paquet de 2 unités)*
7,15 €
(TVA exclue)
8,652 €
(TVA incluse)
Frais de livraison offerts pour toute commande de plus de 75,00 €
Dernier stock RS
- 70 dernière(s) unité(s), prête(s) à l'envoi d'un autre centre de distribution
Unité | Prix par unité | le paquet* |
|---|---|---|
| 2 - 8 | 3,575 € | 7,15 € |
| 10 - 18 | 3,48 € | 6,96 € |
| 20 - 48 | 3,39 € | 6,78 € |
| 50 - 98 | 3,30 € | 6,60 € |
| 100 + | 3,22 € | 6,44 € |
*Prix donné à titre indicatif
- N° de stock RS:
- 216-6204
- Référence fabricant:
- 8305AGILF
- Fabricant:
- Renesas Electronics
Spécifications
Documentation technique
Législations et de normes
Détails du produit
Recherchez des produits similaires en sélectionnant un ou plusieurs attributs.
Sélectionner tout | Attribut | Valeur |
|---|---|---|
| Marque | Renesas Electronics | |
| Logic Function | Clock Buffer | |
| Number of Clock Inputs | 5 | |
| Package Type | TSSOP | |
| Pin Count | 16 | |
| Sélectionner tout | ||
|---|---|---|
Marque Renesas Electronics | ||
Logic Function Clock Buffer | ||
Number of Clock Inputs 5 | ||
Package Type TSSOP | ||
Pin Count 16 | ||
The Renesas Electronics ICS8305I is a low skew, 1-to-4, Differential/LVCMOS-toLVCMOS/LVTTL Fanout Buffer. The ICS8305I has selectable clock inputs that accept either differential or single ended input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. Outputs are forced LOW when the clock is disabled. A separate output enable pin controls whether the outputs are in the active or high impedance state.
4 LVCMOS/LVTTL outputs
Selectable differential or LVCMOS/LVTTL clock inputs
CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
LVCMOS_CLK supports the following input types:
LVCMOS, LVTTL
Maximum output frequency: 350MHz
Output skew: 40ps (maximum)
Part-to-part skew: 700ps (maximum)
Additive phase jitter, RMS: 0.04ps (typical)
3.3V core, 3.3V, 2.5V or 1.8V output operating supply
-40°C to 85°C ambient operating temperature
Lead-Free package fully RoHS compliant
Selectable differential or LVCMOS/LVTTL clock inputs
CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
LVCMOS_CLK supports the following input types:
LVCMOS, LVTTL
Maximum output frequency: 350MHz
Output skew: 40ps (maximum)
Part-to-part skew: 700ps (maximum)
Additive phase jitter, RMS: 0.04ps (typical)
3.3V core, 3.3V, 2.5V or 1.8V output operating supply
-40°C to 85°C ambient operating temperature
Lead-Free package fully RoHS compliant