Renesas Electronics 2309-1HPGG Clock Buffer 16-Pin TSSOP
- N° de stock RS:
- 263-7879
- Référence fabricant:
- 2309-1HPGG
- Fabricant:
- Renesas Electronics
Sous-total (1 tube de 96 unités)*
72,00 €
(TVA exclue)
87,36 €
(TVA incluse)
Frais de livraison offerts pour toute commande de plus de 90,00 €
En stock
- 384 unité(s) prête(s) à être expédiée(s) d'un autre centre de distribution
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Unité | Prix par unité | le tube* |
|---|---|---|
| 96 + | 0,75 € | 72,00 € |
*Prix donné à titre indicatif
- N° de stock RS:
- 263-7879
- Référence fabricant:
- 2309-1HPGG
- Fabricant:
- Renesas Electronics
Spécifications
Documentation technique
Législations et de normes
Détails du produit
Recherchez des produits similaires en sélectionnant un ou plusieurs attributs.
Sélectionner tout | Attribut | Valeur |
|---|---|---|
| Marque | Renesas Electronics | |
| Product Type | Clock Buffer | |
| Maximum Input Frequency | 133MHz | |
| Mount Type | Surface | |
| Package Type | TSSOP | |
| Pin Count | 16 | |
| Minimum Supply Voltage | -0.5V | |
| Maximum Supply Voltage | 4.6V | |
| Minimum Operating Temperature | 0°C | |
| Maximum Operating Temperature | 70°C | |
| Series | IDT2309 | |
| Height | 1mm | |
| Length | 5mm | |
| Standards/Approvals | RoHS | |
| Automotive Standard | No | |
| Sélectionner tout | ||
|---|---|---|
Marque Renesas Electronics | ||
Product Type Clock Buffer | ||
Maximum Input Frequency 133MHz | ||
Mount Type Surface | ||
Package Type TSSOP | ||
Pin Count 16 | ||
Minimum Supply Voltage -0.5V | ||
Maximum Supply Voltage 4.6V | ||
Minimum Operating Temperature 0°C | ||
Maximum Operating Temperature 70°C | ||
Series IDT2309 | ||
Height 1mm | ||
Length 5mm | ||
Standards/Approvals RoHS | ||
Automotive Standard No | ||
The Renesas Electronics high-speed phase-lock loop clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. It is an 8-pin version of the accepts one reference input, and drives out five low skew clocks.
Phase lock loop clock distribution
Distributes one clock input to one bank of five outputs
No external RC network required
Power down mode
Liens connexes
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