Nexperia 74HC595BZX 8-stage Surface Mount Shift Register/Latch 74HC DHXQFN16 p
- N° de stock RS:
- 243-4414
- Référence fabricant:
- 74HC595BZX
- Fabricant:
- Nexperia
Offre groupée disponible
Sous-total (1 paquet de 25 unités)*
5,30 €
(TVA exclue)
6,425 €
(TVA incluse)
Ajouter 500 unités pour bénéficier d'une livraison gratuite
En stock
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Unité | Prix par unité | le paquet* |
|---|---|---|
| 25 - 25 | 0,212 € | 5,30 € |
| 50 - 75 | 0,208 € | 5,20 € |
| 100 - 225 | 0,158 € | 3,95 € |
| 250 - 975 | 0,156 € | 3,90 € |
| 1000 + | 0,097 € | 2,43 € |
*Prix donné à titre indicatif
- N° de stock RS:
- 243-4414
- Référence fabricant:
- 74HC595BZX
- Fabricant:
- Nexperia
Spécifications
Documentation technique
Législations et de normes
Détails du produit
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Sélectionner tout | Attribut | Valeur |
|---|---|---|
| Marque | Nexperia | |
| Package Type | DHXQFN16 p | |
| Logic Function | Shift Register | |
| Number of Stages | 8 | |
| Logic Family | 74HC | |
| Mounting Type | Surface Mount | |
| Sélectionner tout | ||
|---|---|---|
Marque Nexperia | ||
Package Type DHXQFN16 p | ||
Logic Function Shift Register | ||
Number of Stages 8 | ||
Logic Family 74HC | ||
Mounting Type Surface Mount | ||
The Nexperia 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. The device features a serial input (DS) and a serial output (Q7S) to enable cascading and an asynchronous reset MR input. A LOW on MR will reset the shift register. Data is shifted on the LOW-to-HIGH transitions of the SHCP input. The data in the shift register is transferred to the storage register on a LOW-to-HIGH transition of the STCP input. If both clocks are connected together, the shift register will always be one clock pulse ahead of the storage register. Data in the storage register appears at the output whenever the output enable input (OE) is LOW.
Wide supply voltage range from 2.0 to 6.0 V
CMOS low power dissipation
High noise immunity
8-bit serial input
8-bit serial or parallel output
Storage register with 3-state outputs
Shift register with direct clear
100 MHz (typical) shift out frequency
CMOS low power dissipation
High noise immunity
8-bit serial input
8-bit serial or parallel output
Storage register with 3-state outputs
Shift register with direct clear
100 MHz (typical) shift out frequency
A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the registers. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.