Alliance Memory SDRAM 512 MB Surface, 54-Pin 16 bit TSOP
- N° de stock RS:
- 230-8425
- Référence fabricant:
- AS4C32M16SB-7TCN
- Fabricant:
- Alliance Memory
Actuellement indisponible
Désolés, nous ne savons pas quand ce produit sera réapprovisionné.
- N° de stock RS:
- 230-8425
- Référence fabricant:
- AS4C32M16SB-7TCN
- Fabricant:
- Alliance Memory
Spécifications
Documentation technique
Législations et de normes
Détails du produit
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Sélectionner tout | Attribut | Valeur |
|---|---|---|
| Marque | Alliance Memory | |
| Memory Size | 512MB | |
| Product Type | SDRAM | |
| Organisation | 32M x 16 bit | |
| Data Bus Width | 16bit | |
| Address Bus Width | 13bit | |
| Maximum Clock Frequency | 166MHz | |
| Number of Bits per Word | 16 | |
| Maximum Random Access Time | 5.4ns | |
| Number of Words | 8K | |
| Mount Type | Surface | |
| Package Type | TSOP | |
| Pin Count | 54 | |
| Minimum Operating Temperature | 0°C | |
| Maximum Operating Temperature | 70°C | |
| Standards/Approvals | No | |
| Width | 10.29mm | |
| Height | 1.2mm | |
| Length | 22.35mm | |
| Minimum Supply Voltage | 3V | |
| Maximum Supply Voltage | 3.6V | |
| Automotive Standard | No | |
| Sélectionner tout | ||
|---|---|---|
Marque Alliance Memory | ||
Memory Size 512MB | ||
Product Type SDRAM | ||
Organisation 32M x 16 bit | ||
Data Bus Width 16bit | ||
Address Bus Width 13bit | ||
Maximum Clock Frequency 166MHz | ||
Number of Bits per Word 16 | ||
Maximum Random Access Time 5.4ns | ||
Number of Words 8K | ||
Mount Type Surface | ||
Package Type TSOP | ||
Pin Count 54 | ||
Minimum Operating Temperature 0°C | ||
Maximum Operating Temperature 70°C | ||
Standards/Approvals No | ||
Width 10.29mm | ||
Height 1.2mm | ||
Length 22.35mm | ||
Minimum Supply Voltage 3V | ||
Maximum Supply Voltage 3.6V | ||
Automotive Standard No | ||
The Alliance Memory 512Mb SDRAM is a high-speed CMOS synchronous DRAM containing 512 Mbits. It is internally configured as 4 Banks of 8M word x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a Bank Activate command which is then followed by a Read or Write command.
Auto Refresh and Self Refresh
8192 refresh cycles/64ms
CKE power down mode
Single +3.3V ±0.3V power supply
Liens connexes
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