Renesas Electronics 8305AGLF Clock Buffer, 16-Pin 4 TSSOP
- N° de stock RS:
- 216-6206
- Référence fabricant:
- 8305AGLF
- Fabricant:
- Renesas Electronics
Sous-total (1 paquet de 2 unités)*
6,73 €
(TVA exclue)
8,144 €
(TVA incluse)
Frais de livraison offerts pour toute commande de plus de 75,00 €
Dernier stock RS
- 148 dernière(s) unité(s), prête(s) à l'envoi d'un autre centre de distribution
Unité | Prix par unité | le paquet* |
|---|---|---|
| 2 + | 3,365 € | 6,73 € |
*Prix donné à titre indicatif
- N° de stock RS:
- 216-6206
- Référence fabricant:
- 8305AGLF
- Fabricant:
- Renesas Electronics
Spécifications
Documentation technique
Législations et de normes
Détails du produit
Recherchez des produits similaires en sélectionnant un ou plusieurs attributs.
Sélectionner tout | Attribut | Valeur |
|---|---|---|
| Marque | Renesas Electronics | |
| Product Type | Clock Buffer | |
| Mount Type | Surface | |
| Package Type | TSSOP | |
| Pin Count | 16 | |
| Minimum Supply Voltage | 1.5V | |
| Maximum Supply Voltage | 3.3V | |
| Minimum Operating Temperature | 0°C | |
| Maximum Operating Temperature | 70°C | |
| Height | 0.9mm | |
| Length | 4mm | |
| Width | 3.3 mm | |
| Series | 8305A | |
| Standards/Approvals | No | |
| Automotive Standard | No | |
| Number of Outputs | 4 | |
| Sélectionner tout | ||
|---|---|---|
Marque Renesas Electronics | ||
Product Type Clock Buffer | ||
Mount Type Surface | ||
Package Type TSSOP | ||
Pin Count 16 | ||
Minimum Supply Voltage 1.5V | ||
Maximum Supply Voltage 3.3V | ||
Minimum Operating Temperature 0°C | ||
Maximum Operating Temperature 70°C | ||
Height 0.9mm | ||
Length 4mm | ||
Width 3.3 mm | ||
Series 8305A | ||
Standards/Approvals No | ||
Automotive Standard No | ||
Number of Outputs 4 | ||
The Renesas Electronics ICS8305 is a low skew, 1-to-4, Differential/ LVCMOS-to-LVCMOS/LVTTL Fanout Buffer. The ICS8305 has selectable clock inputs that accept either differential or single ended input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. Outputs are forced LOW when the clock is disabled. A separate output enable pin controls whether the outputs are in the active or high impedance state.
Four LVCMOS / LVTTL outputs, 7 output impedance
Selectable differential or LVCMOS / LVTTL clock inputs
CLK, nCLK pair can accept the following differential input levels:
LVPECL, LVDS, LVHSTL, HCSL, SSTL
LVCMOS_CLK supports the following input types: LVCMOS,
LVTTL
Maximum output frequency: 350MHz
Output skew: 35ps (maximum)
Part-to-part skew: 700ps (maximum)
Additive phase jitter, RMS: 0.04ps (typical)