Renesas Electronics 2305-1HDCG Clock Buffer 8-Pin SOIC
- N° de stock RS:
- 263-7866
- Référence fabricant:
- 2305-1HDCG
- Fabricant:
- Renesas Electronics
Sous-total (1 tube de 97 unités)*
36,375 €
(TVA exclue)
44,038 €
(TVA incluse)
Frais de livraison offerts pour toute commande de plus de 75,00 €
En stock
- 1 261 unité(s) prête(s) à être expédiée(s) d'un autre centre de distribution
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Unité | Prix par unité | le tube* |
|---|---|---|
| 97 + | 0,375 € | 36,38 € |
*Prix donné à titre indicatif
- N° de stock RS:
- 263-7866
- Référence fabricant:
- 2305-1HDCG
- Fabricant:
- Renesas Electronics
Spécifications
Documentation technique
Législations et de normes
Détails du produit
Recherchez des produits similaires en sélectionnant un ou plusieurs attributs.
Sélectionner tout | Attribut | Valeur |
|---|---|---|
| Marque | Renesas Electronics | |
| Product Type | Clock Buffer | |
| Maximum Input Frequency | 133MHz | |
| Maximum Propagation Delay Time | 350ps | |
| Mount Type | Surface | |
| Package Type | SOIC | |
| Pin Count | 8 | |
| Number of Outputs | 5 | |
| Minimum Supply Voltage | 3V | |
| Maximum Supply Voltage | 4.6V | |
| Minimum Operating Temperature | -40°C | |
| Maximum Operating Temperature | 85°C | |
| Height | 1.75mm | |
| Standards/Approvals | RoHS | |
| Series | IDT2305 | |
| Width | 4 mm | |
| Length | 5mm | |
| Automotive Standard | No | |
| Sélectionner tout | ||
|---|---|---|
Marque Renesas Electronics | ||
Product Type Clock Buffer | ||
Maximum Input Frequency 133MHz | ||
Maximum Propagation Delay Time 350ps | ||
Mount Type Surface | ||
Package Type SOIC | ||
Pin Count 8 | ||
Number of Outputs 5 | ||
Minimum Supply Voltage 3V | ||
Maximum Supply Voltage 4.6V | ||
Minimum Operating Temperature -40°C | ||
Maximum Operating Temperature 85°C | ||
Height 1.75mm | ||
Standards/Approvals RoHS | ||
Series IDT2305 | ||
Width 4 mm | ||
Length 5mm | ||
Automotive Standard No | ||
The Renesas Electronics high-speed phase-lock loop clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. It is an 8-pin version of the accepts one reference input, and drives out five low skew clocks.
Phase lock loop clock distribution
Distributes one clock input to one bank of five outputs
No external RC network required
Power down mode
Liens connexes
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