Infineon SRAM, CY7C1041G-10ZSXI- 4 MB
- N° de stock RS:
- 273-7349
- Référence fabricant:
- CY7C1041G-10ZSXI
- Fabricant:
- Infineon
Sous-total (1 plateau de 135 unités)*
534,60 €
(TVA exclue)
646,65 €
(TVA incluse)
Frais de livraison offerts pour toute commande de plus de 75,00 €
Temporairement en rupture de stock
- Expédition à partir du 07 juillet 2026
Besoin de plus? Cliquez sur " Vérifier les dates de livraison " pour plus de détails
Unité | Prix par unité | le plateau* |
|---|---|---|
| 135 + | 3,96 € | 534,60 € |
*Prix donné à titre indicatif
- N° de stock RS:
- 273-7349
- Référence fabricant:
- CY7C1041G-10ZSXI
- Fabricant:
- Infineon
Spécifications
Documentation technique
Législations et de normes
Détails du produit
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Sélectionner tout | Attribut | Valeur |
|---|---|---|
| Marque | Infineon | |
| Product Type | SRAM | |
| Memory Size | 4MB | |
| Organisation | 256 K x 16 | |
| Number of Words | 256K | |
| Number of Bits per Word | 16 | |
| Minimum Supply Voltage | 0.5V | |
| Mount Type | Surface | |
| Maximum Supply Voltage | 0.5V | |
| Minimum Operating Temperature | -40°C | |
| Package Type | TSOP II | |
| Maximum Operating Temperature | 85°C | |
| Pin Count | 44 | |
| Standards/Approvals | RoHS | |
| Height | 10.26mm | |
| Width | 1.19 mm | |
| Length | 18.51mm | |
| Series | CY7C1041G | |
| Supply Current | 45mA | |
| Sélectionner tout | ||
|---|---|---|
Marque Infineon | ||
Product Type SRAM | ||
Memory Size 4MB | ||
Organisation 256 K x 16 | ||
Number of Words 256K | ||
Number of Bits per Word 16 | ||
Minimum Supply Voltage 0.5V | ||
Mount Type Surface | ||
Maximum Supply Voltage 0.5V | ||
Minimum Operating Temperature -40°C | ||
Package Type TSOP II | ||
Maximum Operating Temperature 85°C | ||
Pin Count 44 | ||
Standards/Approvals RoHS | ||
Height 10.26mm | ||
Width 1.19 mm | ||
Length 18.51mm | ||
Series CY7C1041G | ||
Supply Current 45mA | ||
The Infineon Static RAM are high performance CMOS fast static RAM device with embedded ECC. This Static RAM device offered in single chip enable option and in multiple pin configurations. This device includes an ERR pin that signals an error detection and correction event during a read cycle. Data writes are performed by asserting the chip enable and write enable inputs LOW, while providing the data on IO 0 through IO 15 and address on A0 through A17 pins. The byte high enable and byte low enable inputs control write operations to the upper and lower bytes of the specified memory location.
High speed
Low active and standby currents
1 bit error detection and correction
TTL compatible inputs and outputs
Embedded ECC for single bit error correction