Alliance Memory AS4C64M8D3L-12BIN SDRAM 512 MB Surface, 96-Pin 8 bit BGA
- N° de stock RS:
- 665-383
- Référence fabricant:
- AS4C64M8D3L-12BIN
- Fabricant:
- Alliance Memory
Indisponible
RS n'aura plus ce produit en stock.
- N° de stock RS:
- 665-383
- Référence fabricant:
- AS4C64M8D3L-12BIN
- Fabricant:
- Alliance Memory
Spécifications
Documentation technique
Législations et de normes
Détails du produit
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Sélectionner tout | Attribut | Valeur |
|---|---|---|
| Marque | Alliance Memory | |
| Product Type | SDRAM | |
| Memory Size | 512MB | |
| Organisation | 64M x 8 | |
| Data Bus Width | 8bit | |
| Number of Bits per Word | 8 | |
| Maximum Clock Frequency | 800MHz | |
| Number of Words | 64 | |
| Mount Type | Surface | |
| Package Type | BGA | |
| Minimum Operating Temperature | -40°C | |
| Pin Count | 96 | |
| Maximum Operating Temperature | 95°C | |
| Width | 8 mm | |
| Height | 1mm | |
| Standards/Approvals | JEDEC, RoHS | |
| Length | 10.5mm | |
| Maximum Supply Voltage | 1.45V | |
| Automotive Standard | No | |
| Minimum Supply Voltage | 1.283V | |
| Sélectionner tout | ||
|---|---|---|
Marque Alliance Memory | ||
Product Type SDRAM | ||
Memory Size 512MB | ||
Organisation 64M x 8 | ||
Data Bus Width 8bit | ||
Number of Bits per Word 8 | ||
Maximum Clock Frequency 800MHz | ||
Number of Words 64 | ||
Mount Type Surface | ||
Package Type BGA | ||
Minimum Operating Temperature -40°C | ||
Pin Count 96 | ||
Maximum Operating Temperature 95°C | ||
Width 8 mm | ||
Height 1mm | ||
Standards/Approvals JEDEC, RoHS | ||
Length 10.5mm | ||
Maximum Supply Voltage 1.45V | ||
Automotive Standard No | ||
Minimum Supply Voltage 1.283V | ||
- Pays d'origine :
- TW
The Alliance Memory 512Mb DDR3L DRAM features a double data rate architecture for high-speed operation and is internally configured as an eight-bank DRAM. It is organized as 8Mbit x8 I/Os x8 banks and supports double-data-rate transfer rates of up to 1600Mb/sec per pin, making it suitable for general-purpose applications. Designed to comply with all key DDR3L specifications, the device ensures synchronized control and address inputs through a pair of externally supplied differential clocks.
8 internal banks for concurrent operation
8n-bit prefect architecture
Pipelined internal architecture
Precharge & active power down
Programmable Mode & Extended Mode registers
Burst type is Sequential and Interleave
Output Driver Impedance Control
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