Toshiba 74VHC21FT, Dual 4-Input AND Logic Gate, 14-Pin TSSOP
- N° de stock RS:
- 171-3329
- Référence fabricant:
- 74VHC21FT
- Fabricant:
- Toshiba
Informations sur le stock actuellement non accessibles
- N° de stock RS:
- 171-3329
- Référence fabricant:
- 74VHC21FT
- Fabricant:
- Toshiba
Spécifications
Documentation technique
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Détails du produit
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Sélectionner tout | Attribut | Valeur |
|---|---|---|
| Marque | Toshiba | |
| Logic Function | AND | |
| Mounting Type | Surface Mount | |
| Number of Elements | 2 | |
| Number of Inputs per Gate | 4 | |
| Package Type | TSSOP | |
| Pin Count | 14 | |
| Logic Family | 74VHC | |
| Input Type | CMOS, TTL | |
| Maximum Operating Supply Voltage | 5.5 V | |
| Maximum High Level Output Current | -8mA | |
| Maximum Propagation Delay Time @ Maximum CL | 13.5 ns @ 50 pF | |
| Minimum Operating Supply Voltage | 2 V | |
| Maximum Low Level Output Current | 8mA | |
| Height | 1mm | |
| Width | 4.4mm | |
| Minimum Operating Temperature | -40 °C | |
| Dimensions | 5 x 4.4 x 1mm | |
| Length | 5mm | |
| Automotive Standard | AEC-Q100 | |
| Output Type | Buffer, CMOS | |
| Maximum Operating Temperature | +125 °C | |
| Propagation Delay Test Condition | 50pF | |
| Sélectionner tout | ||
|---|---|---|
Marque Toshiba | ||
Logic Function AND | ||
Mounting Type Surface Mount | ||
Number of Elements 2 | ||
Number of Inputs per Gate 4 | ||
Package Type TSSOP | ||
Pin Count 14 | ||
Logic Family 74VHC | ||
Input Type CMOS, TTL | ||
Maximum Operating Supply Voltage 5.5 V | ||
Maximum High Level Output Current -8mA | ||
Maximum Propagation Delay Time @ Maximum CL 13.5 ns @ 50 pF | ||
Minimum Operating Supply Voltage 2 V | ||
Maximum Low Level Output Current 8mA | ||
Height 1mm | ||
Width 4.4mm | ||
Minimum Operating Temperature -40 °C | ||
Dimensions 5 x 4.4 x 1mm | ||
Length 5mm | ||
Automotive Standard AEC-Q100 | ||
Output Type Buffer, CMOS | ||
Maximum Operating Temperature +125 °C | ||
Propagation Delay Test Condition 50pF | ||
The 74VHC21FT is an advanced high speed CMOS 4-INPUT AND GATE fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The internal circuit is composed of 4 stages including a buffer output, which provide high noise immunity and stable output. An input protection circuit ensures that 0 to 5.5 V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5 V to 3 V systems and two supply systems such as battery back up. This circuit prevents device destruction due to mismatched supply and input voltages.
Wide operating temperature: Topr = -40 to 125
High speed: tpd = 3.3 ns (typ.) at VCC = 5.0 V
Low power dissipation: ICC = 2.0 μA (max) at Ta = 25
High noise immunity: VNIH = VNIL = 28 % VCC (min)
Power down protection is provided on all inputs.
Balanced propagation delays: tPLH ≈ tPHL
Wide operating voltage range: VCC(opr) = 2.0 V to 5.5 V
Pin and function compatible with the 74 series (AC/HC/AHC/LV etc.) 21 type
High speed: tpd = 3.3 ns (typ.) at VCC = 5.0 V
Low power dissipation: ICC = 2.0 μA (max) at Ta = 25
High noise immunity: VNIH = VNIL = 28 % VCC (min)
Power down protection is provided on all inputs.
Balanced propagation delays: tPLH ≈ tPHL
Wide operating voltage range: VCC(opr) = 2.0 V to 5.5 V
Pin and function compatible with the 74 series (AC/HC/AHC/LV etc.) 21 type