Nexperia 74AUP2G08DC,125, 2 2-Input AND Schmitt Trigger Input Logic Gate, 8-Pin VSSOP
- N° de stock RS:
- 153-2935
- Référence fabricant:
- 74AUP2G08DC,125
- Fabricant:
- Nexperia
Offre groupée disponible
Sous-total (1 paquet de 25 unités)*
5,75 €
(TVA exclue)
7,00 €
(TVA incluse)
Frais de livraison offerts pour toute commande de plus de 75,00 €
Temporairement en rupture de stock
- Expédition à partir du 28 juillet 2026
Besoin de plus? Cliquez sur " Vérifier les dates de livraison " pour plus de détails
Unité | Prix par unité | le paquet* |
|---|---|---|
| 25 - 225 | 0,23 € | 5,75 € |
| 250 - 600 | 0,223 € | 5,58 € |
| 625 - 1225 | 0,218 € | 5,45 € |
| 1250 - 2475 | 0,212 € | 5,30 € |
| 2500 + | 0,206 € | 5,15 € |
*Prix donné à titre indicatif
- N° de stock RS:
- 153-2935
- Référence fabricant:
- 74AUP2G08DC,125
- Fabricant:
- Nexperia
Spécifications
Documentation technique
Législations et de normes
Détails du produit
Recherchez des produits similaires en sélectionnant un ou plusieurs attributs.
Sélectionner tout | Attribut | Valeur |
|---|---|---|
| Marque | Nexperia | |
| Product Type | Logic Gate | |
| Logic Function | AND | |
| Mount Type | Surface | |
| Number of Elements | 2 | |
| Number of Inputs per Gate | 2 | |
| Schmitt Trigger Input | Yes | |
| Package Type | VSSOP | |
| Pin Count | 8 | |
| Logic Family | AUP | |
| Input Type | CMOS | |
| Maximum High Level Output Current | -4mA | |
| Maximum Propagation Delay Time @ CL | 8.3ns | |
| Minimum Operating Temperature | -40°C | |
| Maximum Operating Temperature | 125°C | |
| Maximum Supply Voltage | 3.6V | |
| Height | 0.85mm | |
| Length | 2.1mm | |
| Standards/Approvals | No | |
| Minimum Supply Voltage | 0.8V | |
| Width | 2.4 mm | |
| Series | 74AUP2G | |
| Maximum Low Level Output Current | 4mA | |
| Output Type | ECL | |
| Automotive Standard | No | |
| Sélectionner tout | ||
|---|---|---|
Marque Nexperia | ||
Product Type Logic Gate | ||
Logic Function AND | ||
Mount Type Surface | ||
Number of Elements 2 | ||
Number of Inputs per Gate 2 | ||
Schmitt Trigger Input Yes | ||
Package Type VSSOP | ||
Pin Count 8 | ||
Logic Family AUP | ||
Input Type CMOS | ||
Maximum High Level Output Current -4mA | ||
Maximum Propagation Delay Time @ CL 8.3ns | ||
Minimum Operating Temperature -40°C | ||
Maximum Operating Temperature 125°C | ||
Maximum Supply Voltage 3.6V | ||
Height 0.85mm | ||
Length 2.1mm | ||
Standards/Approvals No | ||
Minimum Supply Voltage 0.8V | ||
Width 2.4 mm | ||
Series 74AUP2G | ||
Maximum Low Level Output Current 4mA | ||
Output Type ECL | ||
Automotive Standard No | ||
Low-power dual 2-input AND gate, The 74AUP2G08 provides the dual 2-input AND function. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down.
Wide supply voltage range from 0.8 V to 3.6 V
High noise immunity
Low static power consumption, ICC = 0.9 μA (maximum)
Latch-up performance exceeds 100 mA per JESD78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of VCC
IOFF circuitry provides partial power-down mode operation
Multiple package options
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