Nexperia 74HC273D,653 8-Bit Latch, Addressable, D Type Flip-Flop, 20-Pin SO
- N° de stock RS:
- 170-7978
- Référence fabricant:
- 74HC273D,653
- Fabricant:
- Nexperia
Sous-total (1 bobine de 2000 unités)*
514,00 €
(TVA exclue)
622,00 €
(TVA incluse)
Ajouter 2000 unités pour bénéficier d'une livraison gratuite
Temporairement en rupture de stock
- Expédition à partir du 01 septembre 2026
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Unité | Prix par unité | la bobine* |
|---|---|---|
| 2000 + | 0,257 € | 514,00 € |
*Prix donné à titre indicatif
- N° de stock RS:
- 170-7978
- Référence fabricant:
- 74HC273D,653
- Fabricant:
- Nexperia
Spécifications
Documentation technique
Législations et de normes
Détails du produit
Recherchez des produits similaires en sélectionnant un ou plusieurs attributs.
Sélectionner tout | Attribut | Valeur |
|---|---|---|
| Marque | Nexperia | |
| Logic Family | 74HC | |
| Product Type | Latch | |
| Logic Function | D Type | |
| Latch Mode | Addressable | |
| Number of Bits | 8 | |
| Output Type | D Type Flip-Flop | |
| Polarity | Non-Inverting | |
| Mount Type | Surface | |
| Minimum Supply Voltage | 2V | |
| Package Type | SO | |
| Maximum Supply Voltage | 6V | |
| Pin Count | 20 | |
| Minimum Operating Temperature | -40°C | |
| Maximum Operating Temperature | 125°C | |
| Standards/Approvals | No | |
| Series | 74HC | |
| Length | 13mm | |
| Width | 7.6 mm | |
| Height | 2.45mm | |
| Automotive Standard | No | |
| Sélectionner tout | ||
|---|---|---|
Marque Nexperia | ||
Logic Family 74HC | ||
Product Type Latch | ||
Logic Function D Type | ||
Latch Mode Addressable | ||
Number of Bits 8 | ||
Output Type D Type Flip-Flop | ||
Polarity Non-Inverting | ||
Mount Type Surface | ||
Minimum Supply Voltage 2V | ||
Package Type SO | ||
Maximum Supply Voltage 6V | ||
Pin Count 20 | ||
Minimum Operating Temperature -40°C | ||
Maximum Operating Temperature 125°C | ||
Standards/Approvals No | ||
Series 74HC | ||
Length 13mm | ||
Width 7.6 mm | ||
Height 2.45mm | ||
Automotive Standard No | ||
The 74HC273, 74HCT273 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A LOW on MR forces the outputs LOW independently of clock and data inputs. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.
Mixed 5 V and 3.3 V applications
Improved signal integrity with integrated termination resistors
High noise immunity
Flow through pin out for easy layout
Wide supply voltage range
Low propagation delay
Overvoltage tolerant input options
Integrated source termination resistor options
Bus hold options
Key applications
Frequency division
Controlled delays
Interface between asynchronous and synchronous systems
Liens connexes
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