Nexperia 74LVC573APW,118 8-Bit Octal D Type Latch, Transparent, 3 State, 20-Pin TSSOP
- N° de stock RS:
- 170-4836
- Référence fabricant:
- 74LVC573APW,118
- Fabricant:
- Nexperia
Actuellement indisponible
Nous ne savons pas si cet article sera de nouveau disponible. RS a l'intention de le retirer de son assortiment sous peu.
- N° de stock RS:
- 170-4836
- Référence fabricant:
- 74LVC573APW,118
- Fabricant:
- Nexperia
Spécifications
Documentation technique
Législations et de normes
Détails du produit
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Sélectionner tout | Attribut | Valeur |
|---|---|---|
| Marque | Nexperia | |
| Product Type | Octal D Type Latch | |
| Logic Family | 74LVC | |
| Latch Mode | Transparent | |
| Logic Function | D Type | |
| Number of Bits | 8 | |
| Number of Channels | 8 | |
| Output Type | 3 State | |
| Polarity | Non-Inverting | |
| Mount Type | Surface | |
| Package Type | TSSOP | |
| Minimum Supply Voltage | 1.2V | |
| Maximum Supply Voltage | 3.6V | |
| Pin Count | 20 | |
| Minimum Operating Temperature | -40°C | |
| Maximum Operating Temperature | 125°C | |
| Length | 6.6mm | |
| Standards/Approvals | No | |
| Height | 950μm | |
| Series | 74LVC | |
| Automotive Standard | No | |
| Sélectionner tout | ||
|---|---|---|
Marque Nexperia | ||
Product Type Octal D Type Latch | ||
Logic Family 74LVC | ||
Latch Mode Transparent | ||
Logic Function D Type | ||
Number of Bits 8 | ||
Number of Channels 8 | ||
Output Type 3 State | ||
Polarity Non-Inverting | ||
Mount Type Surface | ||
Package Type TSSOP | ||
Minimum Supply Voltage 1.2V | ||
Maximum Supply Voltage 3.6V | ||
Pin Count 20 | ||
Minimum Operating Temperature -40°C | ||
Maximum Operating Temperature 125°C | ||
Length 6.6mm | ||
Standards/Approvals No | ||
Height 950μm | ||
Series 74LVC | ||
Automotive Standard No | ||
- Pays d'origine :
- CN
The 74LVC573A consists of eight D-type transparent latches, featuring separate D-type inputs for each latch and 3-state true outputs for bus-oriented applications. A Latch Enable (LE) input and an Output Enable (OE) input are common to all internal latches. When LE is HIGH, data at the Dn inputs enters the latches. In this condition, the latches are transparent, that is, a latch output will change each time its corresponding D-input changes.
Mixed 5 V and 3.3 V applications
Save board space
Low cost Interface solutions
Improved signal integrity for complex layouts
Wide supply voltage range
Low propagation delay
Overvoltage tolerant
Source termination
Low input threshold
CMOS low power
Memory controllers
Backplane interfaces
Liens connexes
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