Toshiba 74HC138D, Decoder, 16-Pin SOIC
- N° de stock RS:
- 171-3556
- Référence fabricant:
- 74HC138D
- Fabricant:
- Toshiba
Offre groupée disponible
Sous-total (1 paquet de 50 unités)*
14,00 €
(TVA exclue)
17,00 €
(TVA incluse)
Frais de livraison offerts pour toute commande de plus de 75,00 €
En stock
- 450 unité(s) prête(s) à être expédiée(s) d'un autre centre de distribution
- Plus 8 500 unité(s) expédiée(s) à partir du 04 mars 2026
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Unité | Prix par unité | le paquet* |
|---|---|---|
| 50 - 100 | 0,28 € | 14,00 € |
| 150 - 450 | 0,249 € | 12,45 € |
| 500 - 950 | 0,224 € | 11,20 € |
| 1000 + | 0,203 € | 10,15 € |
*Prix donné à titre indicatif
- N° de stock RS:
- 171-3556
- Référence fabricant:
- 74HC138D
- Fabricant:
- Toshiba
Spécifications
Documentation technique
Législations et de normes
Détails du produit
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Sélectionner tout | Attribut | Valeur |
|---|---|---|
| Marque | Toshiba | |
| Logic Family | 74HC | |
| Product Type | Decoder | |
| Logic Function | Decoder | |
| Number of Inputs | 3 | |
| Mount Type | Surface | |
| Package Type | SOIC | |
| Number of Outputs | 34 | |
| Pin Count | 16 | |
| Minimum Supply Voltage | 2V | |
| Maximum Supply Voltage | 6V | |
| Minimum Operating Temperature | 125°C | |
| Maximum Operating Temperature | -40°C | |
| Standards/Approvals | No | |
| Width | 4 mm | |
| Height | 1.75mm | |
| Length | 10.2mm | |
| Series | 74HC | |
| Automotive Standard | No | |
| Sélectionner tout | ||
|---|---|---|
Marque Toshiba | ||
Logic Family 74HC | ||
Product Type Decoder | ||
Logic Function Decoder | ||
Number of Inputs 3 | ||
Mount Type Surface | ||
Package Type SOIC | ||
Number of Outputs 34 | ||
Pin Count 16 | ||
Minimum Supply Voltage 2V | ||
Maximum Supply Voltage 6V | ||
Minimum Operating Temperature 125°C | ||
Maximum Operating Temperature -40°C | ||
Standards/Approvals No | ||
Width 4 mm | ||
Height 1.75mm | ||
Length 10.2mm | ||
Series 74HC | ||
Automotive Standard No | ||
The 74HC138D is a high speed CMOS 3-to-8 DECODER fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. When the device is enabled, 3 Binary Select inputs (A, B and C) determine which one of the outputs (Y0 - Y7) will go low. When enable input G1 is held low or either G2A or G2B is held high, decoding function is inhibited and alloutputs go high.G1, G2A, and G2B inputs are provided to ease cascade connection and for use as an address decoder for memory systems. All inputs are equipped with protection circuits against static discharge or transient excess voltage
High speed: tpd = 16 ns (typ.) at VCC = 5 V
Low power dissipation: ICC = 4.0 μA (max) at Ta = 25
Balanced propagation delays: tPLH ≈ tPHL
Wide operating voltage range: VCC(opr) = 2.0 to 6.0 V