Terasic GPIO to HSMC/HSTC Adapter Board for DE3, DE2 P0024
- N° de stock RS:
- 768-9048
- Référence fabricant:
- P0024
- Fabricant:
- Terasic
Offre groupée disponible
Sous-total (1 unité)*
62,49 €
(TVA exclue)
75,61 €
(TVA incluse)
Frais de livraison offerts pour toute commande de plus de 90,00 €
En stock
- 1 unité(s) prête(s) à être expédiée(s) d'un autre centre de distribution
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Unité | Prix par unité |
|---|---|
| 1 - 4 | 62,49 € |
| 5 - 9 | 60,89 € |
| 10 + | 59,37 € |
*Prix donné à titre indicatif
- N° de stock RS:
- 768-9048
- Référence fabricant:
- P0024
- Fabricant:
- Terasic
Spécifications
Documentation technique
Législations et de normes
Détails du produit
Recherchez des produits similaires en sélectionnant un ou plusieurs attributs.
Sélectionner tout | Attribut | Valeur |
|---|---|---|
| Marque | Terasic | |
| Kit Classification | Adapter Board | |
| Product Type | Communication & Wireless Development Tool | |
| For Use With | DE3, DE2 | |
| Kit Name | GPIO to HSMC/HSTC | |
| Interface Type | HSMC, HSTC | |
| Standards/Approvals | RoHS | |
| Sélectionner tout | ||
|---|---|---|
Marque Terasic | ||
Kit Classification Adapter Board | ||
Product Type Communication & Wireless Development Tool | ||
For Use With DE3, DE2 | ||
Kit Name GPIO to HSMC/HSTC | ||
Interface Type HSMC, HSTC | ||
Standards/Approvals RoHS | ||
Terasic GPIO-HSTC Adapter Board
The HTG Card is designed to convert a High-Speed Terasic connector (HSTC) or a High-Speed Mezzanine connector (HSMC) I/Os to three 40-pin expansion prototype connectors, which are compatible with Altera DE3/DE2-115/DE2/DE1/DE0 expansion headers. Users can connect up to three Altera DE3/DE2-115/DE2/DE1/DE0 boards (or associated daughter cards) onto a HSTC/HSMC-interfaced host board via a HTG Card.
Convert HSTC/HSMC-interfaced I/O to standard 40-pin expansion connectors
Allow users to connect Altera DE3/DE2-115/DE2/DE1/DE0 boards to a HSTC/HSMC-interfaced host board
Provide test points for signal measurement
An FPGA is a semiconductor device consisting of a matrix of Configurable Logic Blocks (CLBs) connected through programmable interconnects. The user determines these interconnections by programming SRAM. A CLB can be simple (AND, OR gates, etc) or complex (a block of RAM). The FPGA allows changes to be made to a design even after the device is soldered into a PCB.
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