The Cypress Semiconductor CY7C1354C series are 3.3V, 256K ´ 36 synchronous pipelined burst SRAMs with no bus latency logic, respectively. They are designed to support unlimited true back-to-back read/write operations with no wait states. It is equipped with the advanced logic required to enable consecutive read/write operations with data being transferred on every clock cycle.
Pin-compatible and functionally equivalent to ZBT Supports 250 MHz bus operations with zero wait states Available speed grades are 250, 200, and 166 MHz Internally self-timed output buffer control to eliminate the need to use asynchronous OE Fully registered for pipelined operation Byte write capability
