Winbond W9712G6KB25I DDR2 SDRAM 128 MB Surface, 84-Pin 16 bit TFBGA

Offre groupée disponible

Sous-total (1 paquet de 5 unités)*

11,16 €

(TVA exclue)

13,505 €

(TVA incluse)

Add to Basket
sélectionner ou taper la quantité
Temporairement en rupture de stock
  • Expédition à partir du 26 août 2026
Besoin de plus? Cliquez sur " Vérifier les dates de livraison " pour plus de détails

Unité
Prix par unité
le paquet*
5 - 52,232 €11,16 €
10 - 152,03 €10,15 €
20 - 451,992 €9,96 €
50 - 951,968 €9,84 €
100 +1,766 €8,83 €

*Prix donné à titre indicatif

Options de conditionnement :
N° de stock RS:
188-2730
Référence fabricant:
W9712G6KB25I
Fabricant:
Winbond
Recherchez des produits similaires en sélectionnant un ou plusieurs attributs.
Sélectionner tout

Marque

Winbond

Memory Size

128MB

Product Type

DDR2 SDRAM

Data Bus Width

16bit

Address Bus Width

15bit

Number of Bits per Word

8

Maximum Random Access Time

0.4ns

Number of Words

16M

Mount Type

Surface

Package Type

TFBGA

Minimum Operating Temperature

-40°C

Pin Count

84

Maximum Operating Temperature

95°C

Series

W9712G6KB

Standards/Approvals

RoHS

Length

12.6mm

Height

0.8mm

Maximum Supply Voltage

1.9V

Supply Current

135mA

Automotive Standard

No

Minimum Supply Voltage

1.7V

The W9712G6KB is a 128M bits DDR2 SDRAM and speed involving -25, 25I and -3.

Double Data Rate architecture: two data transfers per clock cycle

CAS Latency: 3, 4, 5 and 6

Burst Length: 4 and 8

Bi-directional, differential data strobes (DQS and /DQS ) are transmitted / received with data

Edge-aligned with Read data and center-aligned with Write data

DLL aligns DQ and DQS transitions with clock

Differential clock inputs (CLK and /CLK)

Data masks (DM) for write data

Commands entered on each positive CLK edge, data and data mask are referenced to both edges of /DQS

Posted /CAS programmable additive latency supported to make command and data bus efficiency

Read Latency = Additive Latency plus CAS Latency (RL = AL + CL)

Off-Chip-Driver impedance adjustment (OCD) and On-Die-Termination (ODT) for better signal quality

Auto-precharge operation for read and write bursts

Auto Refresh and Self Refresh modes

Precharged Power Down and Active Power Down

Write Data Mask

Write Latency = Read Latency - 1 (WL = RL - 1)

Interface: SSTL_18

Liens connexes