Alliance Memory AS4C512M16MD4V-053BIN SDRAM 8 GB Surface, 200-Pin 16 bit TFBGA
- N° de stock RS:
- 665-385
- Référence fabricant:
- AS4C512M16MD4V-053BIN
- Fabricant:
- Alliance Memory
Sous-total (1 unité)*
43,90 €
(TVA exclue)
53,12 €
(TVA incluse)
Frais de livraison offerts pour toute commande de plus de 75,00 €
En stock
- Plus 120 unité(s) expédiée(s) à partir du 16 mars 2026
Besoin de plus? Cliquez sur " Vérifier les dates de livraison " pour plus de détails
Unité | Prix par unité |
|---|---|
| 1 + | 43,90 € |
*Prix donné à titre indicatif
- N° de stock RS:
- 665-385
- Référence fabricant:
- AS4C512M16MD4V-053BIN
- Fabricant:
- Alliance Memory
Spécifications
Documentation technique
Législations et de normes
Détails du produit
Recherchez des produits similaires en sélectionnant un ou plusieurs attributs.
Sélectionner tout | Attribut | Valeur |
|---|---|---|
| Marque | Alliance Memory | |
| Memory Size | 8GB | |
| Product Type | SDRAM | |
| Organisation | 512M x 16 | |
| Data Bus Width | 16bit | |
| Address Bus Width | 6bit | |
| Number of Bits per Word | 32 | |
| Mount Type | Surface | |
| Package Type | TFBGA | |
| Pin Count | 200 | |
| Minimum Operating Temperature | -40°C | |
| Maximum Operating Temperature | 95°C | |
| Length | 15mm | |
| Standards/Approvals | No | |
| Height | 1mm | |
| Automotive Standard | No | |
| Maximum Supply Voltage | 1.8V | |
| Minimum Supply Voltage | 0.6V | |
| Sélectionner tout | ||
|---|---|---|
Marque Alliance Memory | ||
Memory Size 8GB | ||
Product Type SDRAM | ||
Organisation 512M x 16 | ||
Data Bus Width 16bit | ||
Address Bus Width 6bit | ||
Number of Bits per Word 32 | ||
Mount Type Surface | ||
Package Type TFBGA | ||
Pin Count 200 | ||
Minimum Operating Temperature -40°C | ||
Maximum Operating Temperature 95°C | ||
Length 15mm | ||
Standards/Approvals No | ||
Height 1mm | ||
Automotive Standard No | ||
Maximum Supply Voltage 1.8V | ||
Minimum Supply Voltage 0.6V | ||
- Pays d'origine :
- KR
The Alliance Memory 8Gb (x16) LPDDR4X DRAM in a 200-ball FBGA package features a double-data rate architecture enabling two data transfers per clock cycle. Commands and addresses are latched on the positive edges of CK, while data and data mask signals are referenced to both edges of DQS. It includes 8 internal banks per channel and supports CA calibration, internal VREF with VREF training, and FIFO-based write/read training. Additionally, it offers MPC (Multi Purpose Command) functionality for enhanced control and flexibility.
Auto Precharge option for each burst access
Configurable Drive Strength
Refresh and Self Refresh Modes
Write Leveling
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