Alliance Memory AS4C1G8D4A-62BIN SDRAM 1 GB Surface, 78-Pin 8 bit FBGA
- N° de stock RS:
- 665-384
- Référence fabricant:
- AS4C1G8D4A-62BIN
- Fabricant:
- Alliance Memory
Sous-total (1 unité)*
66,67 €
(TVA exclue)
80,67 €
(TVA incluse)
Frais de livraison offerts pour toute commande de plus de 90,00 €
Dernier stock RS
- 209 dernière(s) unité(s), prête(s) à l'envoi d'un autre centre de distribution
Unité | Prix par unité |
|---|---|
| 1 + | 66,67 € |
*Prix donné à titre indicatif
- N° de stock RS:
- 665-384
- Référence fabricant:
- AS4C1G8D4A-62BIN
- Fabricant:
- Alliance Memory
Spécifications
Documentation technique
Législations et de normes
Détails du produit
Recherchez des produits similaires en sélectionnant un ou plusieurs attributs.
Sélectionner tout | Attribut | Valeur |
|---|---|---|
| Marque | Alliance Memory | |
| Memory Size | 1GB | |
| Product Type | SDRAM | |
| Data Bus Width | 8bit | |
| Maximum Clock Frequency | 1600MHz | |
| Number of Bits per Word | 8 | |
| Mount Type | Surface | |
| Package Type | FBGA | |
| Pin Count | 78 | |
| Minimum Operating Temperature | -40°C | |
| Maximum Operating Temperature | 95°C | |
| Standards/Approvals | JEDEC, RoHS | |
| Height | 1.2mm | |
| Length | 12mm | |
| Minimum Supply Voltage | 1.14V | |
| Automotive Standard | No | |
| Maximum Supply Voltage | 1.26V | |
| Sélectionner tout | ||
|---|---|---|
Marque Alliance Memory | ||
Memory Size 1GB | ||
Product Type SDRAM | ||
Data Bus Width 8bit | ||
Maximum Clock Frequency 1600MHz | ||
Number of Bits per Word 8 | ||
Mount Type Surface | ||
Package Type FBGA | ||
Pin Count 78 | ||
Minimum Operating Temperature -40°C | ||
Maximum Operating Temperature 95°C | ||
Standards/Approvals JEDEC, RoHS | ||
Height 1.2mm | ||
Length 12mm | ||
Minimum Supply Voltage 1.14V | ||
Automotive Standard No | ||
Maximum Supply Voltage 1.26V | ||
- Pays d'origine :
- TW
The Alliance Memory 8Gb DDR4 DRAM in a 78-ball FBGA package supports JEDEC clock jitter specifications and features a bidirectional differential data strobe along with differential clocks. It is internally organized into 16 banks, grouped as four sets of four banks each, with separated I/O gating structures by bank group. The device uses an 8n-bit prefect architecture and supports power-saving features such as precharge and active power-down, auto refresh, self refresh, low-power auto self refresh (LPASR), self refresh abort, and fine granularity refresh, ensuring efficient and high-performance operation.
Internal VREFDQ Training
Read Preamble Training
Control Gear Down Mode
Per DRAM Addressability
Output Driver Impedance Control
Dynamic on-die termination
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