ISSI IS42S32800J-7TLI SDRAM 8 MB Surface, 86-Pin 32 bit TSOP II
- N° de stock RS:
- 648-104
- Référence fabricant:
- IS42S32800J-7TLI
- Fabricant:
- ISSI
Sous-total (1 unité)*
15,20 €
(TVA exclue)
18,39 €
(TVA incluse)
Frais de livraison offerts pour toute commande de plus de 90,00 €
Temporairement en rupture de stock
- Expédition à partir du 12 novembre 2026
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Unité | Prix par unité |
|---|---|
| 1 + | 15,20 € |
*Prix donné à titre indicatif
- N° de stock RS:
- 648-104
- Référence fabricant:
- IS42S32800J-7TLI
- Fabricant:
- ISSI
Spécifications
Documentation technique
Législations et de normes
Détails du produit
Recherchez des produits similaires en sélectionnant un ou plusieurs attributs.
Sélectionner tout | Attribut | Valeur |
|---|---|---|
| Marque | ISSI | |
| Product Type | SDRAM | |
| Memory Size | 8MB | |
| Organisation | 8M x 32 bit | |
| Data Bus Width | 32bit | |
| Maximum Clock Frequency | 143MHz | |
| Maximum Random Access Time | 7ns | |
| Mount Type | Surface | |
| Package Type | TSOP II | |
| Pin Count | 86 | |
| Minimum Operating Temperature | -40°C | |
| Maximum Operating Temperature | 85°C | |
| Standards/Approvals | RoHS | |
| Series | IS42S32800J | |
| Maximum Supply Voltage | 3.6V | |
| Automotive Standard | No | |
| Minimum Supply Voltage | 3.3V | |
| Supply Current | 140mA | |
| Sélectionner tout | ||
|---|---|---|
Marque ISSI | ||
Product Type SDRAM | ||
Memory Size 8MB | ||
Organisation 8M x 32 bit | ||
Data Bus Width 32bit | ||
Maximum Clock Frequency 143MHz | ||
Maximum Random Access Time 7ns | ||
Mount Type Surface | ||
Package Type TSOP II | ||
Pin Count 86 | ||
Minimum Operating Temperature -40°C | ||
Maximum Operating Temperature 85°C | ||
Standards/Approvals RoHS | ||
Series IS42S32800J | ||
Maximum Supply Voltage 3.6V | ||
Automotive Standard No | ||
Minimum Supply Voltage 3.3V | ||
Supply Current 140mA | ||
- Pays d'origine :
- CN
The ISSI 256Mb SDRAM is a high-speed CMOS dynamic random-access memory designed for 3.3V Vdd and 3.3V Vddq systems, containing 268435456 bits. It is internally organized as a quad-bank DRAM with a synchronous interface, with each 67108864-bit bank arranged as 4096 rows by 512 columns by 32 bits. The device supports AUTO REFRESH mode and a power-saving power-down mode. All signals are registered on the positive edge of the clock signal CLK.
LVTTL Interface
Auto Refresh (CBR)
Self Refresh
Liens connexes
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