Alliance Memory AS4C128M8D3LC-12BINTR SDRAM 1 GB Surface, 78-Pin 8 bit FBGA-78 Ball
- N° de stock RS:
- 425-159
- Référence fabricant:
- AS4C128M8D3LC-12BINTR
- Fabricant:
- Alliance Memory
Sous-total (1 bobine de 2500 unités)*
13 230,00 €
(TVA exclue)
16 007,50 €
(TVA incluse)
Informations sur le stock actuellement non accessibles - Veuillez vérifier plus tard
Unité | Prix par unité | la bobine* |
|---|---|---|
| 2500 + | 5,292 € | 13 230,00 € |
*Prix donné à titre indicatif
- N° de stock RS:
- 425-159
- Référence fabricant:
- AS4C128M8D3LC-12BINTR
- Fabricant:
- Alliance Memory
Spécifications
Documentation technique
Législations et de normes
Détails du produit
Recherchez des produits similaires en sélectionnant un ou plusieurs attributs.
Sélectionner tout | Attribut | Valeur |
|---|---|---|
| Marque | Alliance Memory | |
| Memory Size | 1GB | |
| Product Type | SDRAM | |
| Data Bus Width | 8bit | |
| Number of Bits per Word | 8 | |
| Maximum Clock Frequency | 800MHz | |
| Maximum Random Access Time | 20ns | |
| Mount Type | Surface | |
| Package Type | FBGA-78 Ball | |
| Minimum Operating Temperature | -40°C | |
| Pin Count | 78 | |
| Maximum Operating Temperature | 95°C | |
| Standards/Approvals | RoHS, JEDEC | |
| Series | AS4C128M8D3LC | |
| Length | 10.5mm | |
| Height | 1mm | |
| Maximum Supply Voltage | 1.35V | |
| Minimum Supply Voltage | 1.283V | |
| Automotive Standard | No | |
| Sélectionner tout | ||
|---|---|---|
Marque Alliance Memory | ||
Memory Size 1GB | ||
Product Type SDRAM | ||
Data Bus Width 8bit | ||
Number of Bits per Word 8 | ||
Maximum Clock Frequency 800MHz | ||
Maximum Random Access Time 20ns | ||
Mount Type Surface | ||
Package Type FBGA-78 Ball | ||
Minimum Operating Temperature -40°C | ||
Pin Count 78 | ||
Maximum Operating Temperature 95°C | ||
Standards/Approvals RoHS, JEDEC | ||
Series AS4C128M8D3LC | ||
Length 10.5mm | ||
Height 1mm | ||
Maximum Supply Voltage 1.35V | ||
Minimum Supply Voltage 1.283V | ||
Automotive Standard No | ||
- Pays d'origine :
- TW
The Alliance Memory 1Gb Double-Data-Rate-3 DRAMs is double data rate architecture to achieve high-speed operation. The chip is designed to comply with all key DDR3 DRAM key features and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks.
Write Leveling
ZQ Calibration
RoHS compliant
Auto Refresh and Self Refresh
Liens connexes
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