STMicroelectronics STM32MP235CAJ3 ARM Cortex A35, ARM Cortex M33 Microprocessor STM32MP23xC/F 16 bit 32 Bit, 64 Bit, ARM
- N° de stock RS:
- 482-993
- Référence fabricant:
- STM32MP235CAJ3
- Fabricant:
- STMicroelectronics
Visuel non contractuel
Offre groupée disponible
Sous-total (1 unité)*
30,13 €
(TVA exclue)
36,46 €
(TVA incluse)
Ajouter 3 unités pour bénéficier d'une livraison gratuite
Temporairement en rupture de stock
- Expédition à partir du 01 septembre 2026
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Unité | Prix par unité |
|---|---|
| 1 - 4 | 30,13 € |
| 5 + | 29,23 € |
*Prix donné à titre indicatif
- N° de stock RS:
- 482-993
- Référence fabricant:
- STM32MP235CAJ3
- Fabricant:
- STMicroelectronics
Spécifications
Documentation technique
Législations et de normes
Détails du produit
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Sélectionner tout | Attribut | Valeur |
|---|---|---|
| Marque | STMicroelectronics | |
| Product Type | Microprocessor | |
| Series | STM32MP23xC/F | |
| Device Core | ARM Cortex A35, ARM Cortex M33 | |
| Data Bus Width | 16bit | |
| Instruction Set Architecture | 32 Bit, 64 Bit, ARM V8-A, ARM V8-M | |
| Maximum Clock Frequency | 1.5GHz | |
| Interface Type | SPI, FMC Parallel, NAND, LPDDR4, DDR3L, DDR4 | |
| Package Type | TFBGA361 | |
| Minimum Supply Voltage | 1.71V | |
| Pin Count | 361 | |
| Maximum Supply Voltage | 3.6V | |
| Standards/Approvals | JEDEC | |
| Automotive Standard | No | |
| Number of Cores | 2 | |
| Sélectionner tout | ||
|---|---|---|
Marque STMicroelectronics | ||
Product Type Microprocessor | ||
Series STM32MP23xC/F | ||
Device Core ARM Cortex A35, ARM Cortex M33 | ||
Data Bus Width 16bit | ||
Instruction Set Architecture 32 Bit, 64 Bit, ARM V8-A, ARM V8-M | ||
Maximum Clock Frequency 1.5GHz | ||
Interface Type SPI, FMC Parallel, NAND, LPDDR4, DDR3L, DDR4 | ||
Package Type TFBGA361 | ||
Minimum Supply Voltage 1.71V | ||
Pin Count 361 | ||
Maximum Supply Voltage 3.6V | ||
Standards/Approvals JEDEC | ||
Automotive Standard No | ||
Number of Cores 2 | ||
- Pays d'origine :
- TW
The STMicroelectronics MPU with Dual Arm Cortex-A35 devices are based on the high-performance single or dual-core Arm Cortex-A35 64-bit RISC core operating at up to 1.5 GHz. The Cortex‑A35 processor includes a 32-Kbyte L1 instruction cache for each CPU, a 32-Kbyte L1 data cache for each CPU, and a 512-Kbyte L2 cache. The Cortex‑A35 processor uses a highly efficient 8-stage in-order pipeline that has been extensively optimized to provide full Armv8-A features while maximizing area and power efficiency.
Internal temperature sensors
Low power consumption
Clock management
Digital parallel interface up to 16 bit input or output
Two Octo-SPI memory interfaces
DDR memory retention in Standby mode
Controls for PMIC companion chip
Liens connexes
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