NXP LPC11U14FHI33/201, 32 bit ARM Cortex M0, LPC11U Microcontroller, 50 MHz, 32kB FLASH, 33-Pin QFN
- N° de stock RS:
- 791-8138P
- Référence fabricant:
- LPC11U14FHI33/201,
- Fabricant:
- NXP
Sous-total 50 unités (conditionné en plateau)*
213,20 €
(TVA exclue)
257,95 €
(TVA incluse)
Frais de livraison offerts pour toute commande de plus de 90,00 €
- Expédition à partir du 09 février 2027
Unité | Prix par unité |
|---|---|
| 50 - 95 | 4,264 € |
| 100 + | 3,934 € |
*Prix donné à titre indicatif
- N° de stock RS:
- 791-8138P
- Référence fabricant:
- LPC11U14FHI33/201,
- Fabricant:
- NXP
Sélectionner tout | Attribut | Valeur |
|---|---|---|
| Marque | NXP | |
| Product Type | Microcontroller | |
| Series | LPC11U | |
| Package Type | QFN | |
| Mount Type | Surface | |
| Pin Count | 33 | |
| Device Core | ARM Cortex M0 | |
| Data Bus Width | 32bit | |
| Program Memory Size | 32kB | |
| Maximum Clock Frequency | 50MHz | |
| RAM Size | 6kB | |
| Maximum Supply Voltage | 3.6V | |
| Number of Programmable I/Os | 26 | |
| Minimum Operating Temperature | -40°C | |
| Maximum Operating Temperature | 85°C | |
| Width | 5.1mm | |
| Standards/Approvals | RoHS, REACH | |
| Height | 0.85mm | |
| Length | 5.1mm | |
| Minimum Supply Voltage | 1.8V | |
| ADCs | 8 x 10 Bit | |
| Program Memory Type | FLASH | |
| Number of Timers | 4 | |
| Instruction Set Architecture | RISC | |
| Sélectionner tout | ||
|---|---|---|
Marque NXP | ||
Product Type Microcontroller | ||
Series LPC11U | ||
Package Type QFN | ||
Mount Type Surface | ||
Pin Count 33 | ||
Device Core ARM Cortex M0 | ||
Data Bus Width 32bit | ||
Program Memory Size 32kB | ||
Maximum Clock Frequency 50MHz | ||
RAM Size 6kB | ||
Maximum Supply Voltage 3.6V | ||
Number of Programmable I/Os 26 | ||
Minimum Operating Temperature -40°C | ||
Maximum Operating Temperature 85°C | ||
Width 5.1mm | ||
Standards/Approvals RoHS, REACH | ||
Height 0.85mm | ||
Length 5.1mm | ||
Minimum Supply Voltage 1.8V | ||
ADCs 8 x 10 Bit | ||
Program Memory Type FLASH | ||
Number of Timers 4 | ||
Instruction Set Architecture RISC | ||
