Références fabricant

Microchip, 128-Pin PQFP, Switch IC, 3.3 V 100 Mbps 3.3V KSZ8895MQXI

Name: Microchip, 128-Pin PQFP, Switch IC, 3.3 V 100 Mbps 3.3V KSZ8895MQXI
Brand: Microchip
SKU: 177-4010
Availability: InStock

Offre groupée disponible

Consulter les options de prix de gros

Sous-total (1 paquet de 2 unités)*

14,69 €

(TVA exclue)

17,77 €

(TVA incluse)

Informations sur le stock actuellement non accessibles - Veuillez vérifier plus tard

*Prix donné à titre indicatif

Spécifications

Documentation technique

Législations et de normes

Détails du produit

Recherchez des produits similaires en sélectionnant un ou plusieurs attributs.

Sélectionner tout	Attribut	Valeur
	Marque	Microchip
	Maximum Data Rate	100Mbps
	Product Type	Switch IC
	Sub Type	Switch
	Number of Ports	5
	Standard Supported	IEEE 802.1Q
	Mount Type	Surface
	Package Type	PQFP
	Maximum Supply Voltage	3.3V
	Pin Count	128
	Minimum Operating Temperature	-40°C
	Maximum Operating Temperature	85°C
	Standards/Approvals	No
	Length	20mm
	Minimum Supply Voltage	3.3V
	Width	14mm
	Height	3.4mm
	Automotive Standard	No

	Sélectionner tout
	Marque Microchip
	Maximum Data Rate 100Mbps
	Product Type Switch IC
	Sub Type Switch
	Number of Ports 5
	Standard Supported IEEE 802.1Q
	Mount Type Surface
	Package Type PQFP
	Maximum Supply Voltage 3.3V
	Pin Count 128
	Minimum Operating Temperature -40°C
	Maximum Operating Temperature 85°C
	Standards/Approvals No
	Length 20mm
	Minimum Supply Voltage 3.3V
	Width 14mm
	Height 3.4mm
	Automotive Standard No

The KSZ8895MQX/RQX/FQX/ML is a highly-integrated, Layer 2 managed, five-port switch with numerous features designed to reduce system cost.

Advanced Switch Features

VLAN support for up to 128 active VLAN groups (full-range 4096 of VLAN IDs)

Static MAC table supports up to 32 entries

VLAN ID tag/untag options, per port basis

Comprehensive Configuration Register Access

Serial management interface (MDC/MDIO) to all PHYs registers and SMI interface (MDC/MDIO) to all registers

High-speed SPI (up to 25MHz) and I2C master Interface to all internal registers

I/0 pins strapping and EEPROM to program selective registers in unmanaged switch mode

QoS/CoS Packet Prioritization Support

Per port, 802.1p and DiffServ-based

1/2/4-queue QoS prioritization selection

Programmable weighted fair queuing for ratio control

Integrated 5-Port 10/100 Ethernet Switch

New generation switch with five MACs and five PHYs

PHYs designed with patented enhanced mixed-signal technology

Liens connexes