KSZ8081RNACA Microchip Physical Layer Transceiver 100 Mbps, 3.3 V, 24-Pin QFN
- N° de stock RS:
- 215-3274
- Référence fabricant:
- KSZ8081RNACA
- Fabricant:
- Microchip
Sous-total (1 plateau de 490 unités)*
409,15 €
(TVA exclue)
494,90 €
(TVA incluse)
Frais de livraison offerts pour toute commande de plus de 90,00 €
En stock
- Plus 14 210 unité(s) expédiée(s) à partir du 20 avril 2026
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Unité | Prix par unité | le plateau* |
|---|---|---|
| 490 + | 0,835 € | 409,15 € |
*Prix donné à titre indicatif
- N° de stock RS:
- 215-3274
- Référence fabricant:
- KSZ8081RNACA
- Fabricant:
- Microchip
Spécifications
Documentation technique
Législations et de normes
Détails du produit
Recherchez des produits similaires en sélectionnant un ou plusieurs attributs.
Sélectionner tout | Attribut | Valeur |
|---|---|---|
| Marque | Microchip | |
| Product Type | Physical Layer Transceiver | |
| Maximum Data Rate | 100Mbps | |
| Package Type | QFN | |
| Data Rate | 100Mbps | |
| Maximum Input Current | 10μA | |
| Rise Time | 300μs | |
| Number of Pins | 24 | |
| Mount Type | Surface Mount | |
| Maximum Operating Temperature | 70°C | |
| Minimum Operating Temperature | 0°C | |
| Depth | 0.9mm | |
| Standards/Approvals | CAT-5 | |
| Length | 4mm | |
| Series | KSZ8081 | |
| Package Style | QFN | |
| Automotive Standard | No | |
| Sélectionner tout | ||
|---|---|---|
Marque Microchip | ||
Product Type Physical Layer Transceiver | ||
Maximum Data Rate 100Mbps | ||
Package Type QFN | ||
Data Rate 100Mbps | ||
Maximum Input Current 10μA | ||
Rise Time 300μs | ||
Number of Pins 24 | ||
Mount Type Surface Mount | ||
Maximum Operating Temperature 70°C | ||
Minimum Operating Temperature 0°C | ||
Depth 0.9mm | ||
Standards/Approvals CAT-5 | ||
Length 4mm | ||
Series KSZ8081 | ||
Package Style QFN | ||
Automotive Standard No | ||
The Microchip KSZ8081RNA/RND is a single-supply 10BASE-T/100BASE-TX Ethernet physical-layer transceiver for transmission and reception of data over standard CAT-5 unshielded twisted pair (UTP) cable. It is a highly-integrated PHY solution. It reduces board cost and simplifies board layout by using on-chip termination resistors for the differential pairs and by integrating a low-noise regulator to supply the 1.2V core, and by offering 1.8/2.5/3.3V digital I/O Interface support.
Single-Chip 10BASE-T/100BASE-TX IEEE 802.3
Compliant Ethernet Transceiver
RMII v1.2 Interface Support with a 50 MHz Reference Clock Output to MAC, and an Option to Input a 50 MHz Reference Clock
RMII Back-to-Back Mode Support for a 100 Mbps Copper Repeater
MDC/MDIO Management Interface for PHY Register Configuration
Programmable Interrupt Output
LED Outputs for Link and Activity Status Indication
Liens connexes
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