9FGV0441AKLF, Function Generator IC, 32-Pin VFQFPN
- N° de stock RS:
- 216-6272
- Référence fabricant:
- 9FGV0441AKLF
- Fabricant:
- Renesas Electronics
Sous-total (1 plateau de 490 unités)*
859,46 €
(TVA exclue)
1 039,78 €
(TVA incluse)
Frais de livraison offerts pour toute commande de plus de 75,00 €
En stock
- Plus 980 unité(s) expédiée(s) à partir du 23 janvier 2026
Besoin de plus? Cliquez sur " Vérifier les dates de livraison " pour plus de détails
Unité | Prix par unité | le plateau* |
|---|---|---|
| 490 + | 1,754 € | 859,46 € |
*Prix donné à titre indicatif
- N° de stock RS:
- 216-6272
- Référence fabricant:
- 9FGV0441AKLF
- Fabricant:
- Renesas Electronics
Spécifications
Documentation technique
Législations et de normes
Détails du produit
Recherchez des produits similaires en sélectionnant un ou plusieurs attributs.
Sélectionner tout | Attribut | Valeur |
|---|---|---|
| Marque | Renesas Electronics | |
| Mounting Type | Surface Mount | |
| Package Type | VFQFPN | |
| Pin Count | 32 | |
| Sélectionner tout | ||
|---|---|---|
Marque Renesas Electronics | ||
Mounting Type Surface Mount | ||
Package Type VFQFPN | ||
Pin Count 32 | ||
The Renesas Electronics 9FGV0441 is an 4-output very low power clock generator for PCIe Gen 1, 2, 3 and 4 applications with integrated output terminations providing Zo = 100. The device has 4 output enables for clock management and supports 2 different spread spectrum levels in addition to spread off.
Integrated terminations provide 100 differential Zo
reduced component count and board space
1.8V operation
reduced power consumption
OE# pins
OE# pins
support DIF power management
LP-HCSL differential clock outputs
LP-HCSL differential clock outputs
reduced power and
board space
Programmable slew rate for each output
board space
Programmable slew rate for each output
allows tuning
for various line lengths
Programmable output amplitude
for various line lengths
Programmable output amplitude
allows tuning for
various application environments
DIF outputs blocked until PLL is locked
various application environments
DIF outputs blocked until PLL is locked
clean system
start-up
Selectable 0%, -0.25% or -0.5% spread on DIF outputs
start-up
Selectable 0%, -0.25% or -0.5% spread on DIF outputs
reduces EMI
External 25MHz crystal
supports tight ppm with 0 ppm
synthesis error
synthesis error
