854S006AGILF, Clock Buffer LVDS, 2-Input, 24-Pin SOIC
- N° de stock RS:
- 216-6213
- Référence fabricant:
- 854S006AGILF
- Fabricant:
- Renesas Electronics
Sous-total (1 tube de 62 unités)*
1 191,516 €
(TVA exclue)
1 441,748 €
(TVA incluse)
Frais de livraison offerts pour toute commande de plus de 75,00 €
En stock
- Plus 62 unité(s) expédiée(s) à partir du 26 janvier 2026
Besoin de plus? Cliquez sur " Vérifier les dates de livraison " pour plus de détails
Unité | Prix par unité | le tube* |
|---|---|---|
| 62 + | 19,218 € | 1 191,52 € |
*Prix donné à titre indicatif
- N° de stock RS:
- 216-6213
- Référence fabricant:
- 854S006AGILF
- Fabricant:
- Renesas Electronics
Spécifications
Documentation technique
Législations et de normes
Détails du produit
Recherchez des produits similaires en sélectionnant un ou plusieurs attributs.
Sélectionner tout | Attribut | Valeur |
|---|---|---|
| Marque | Renesas Electronics | |
| Logic Family | LVDS | |
| Logic Function | Clock Buffer | |
| Input Signal Type | LVDS | |
| Number of Clock Inputs | 2 | |
| Package Type | SOIC | |
| Pin Count | 24 | |
| Sélectionner tout | ||
|---|---|---|
Marque Renesas Electronics | ||
Logic Family LVDS | ||
Logic Function Clock Buffer | ||
Input Signal Type LVDS | ||
Number of Clock Inputs 2 | ||
Package Type SOIC | ||
Pin Count 24 | ||
The Renesas Electronics 854S006 is a low skew, high performance 1-to-6, Differential-to-LVDS fanout buffer. The CLK, nCLK pair can accept most standard differential input levels. The 854S006 is characterized to operate from either a 2.5V or a 3.3V power supply. Guaranteed output and part-to-part skew characteristics make the 854S006 ideal for those clock distribution applications demanding well defined performance and repeatability.
Six differential LVDS outputs
One differential clock input pair
CLK, nCLK pair can accept the following differential input
levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
Maximum output frequency: 1.7GHz
Translates any single-ended input signal to LVDS levels with
resistor bias on nCLK input
Output Skew: 55ps (maximum)
Propagation delay: 850ps (maximum)
Additive phase jitter, RMS: 0.067ps (typical)
Full 3.3V or 2.5V supply
-40°C to 85°C ambient operating temperature
One differential clock input pair
CLK, nCLK pair can accept the following differential input
levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
Maximum output frequency: 1.7GHz
Translates any single-ended input signal to LVDS levels with
resistor bias on nCLK input
Output Skew: 55ps (maximum)
Propagation delay: 850ps (maximum)
Additive phase jitter, RMS: 0.067ps (typical)
Full 3.3V or 2.5V supply
-40°C to 85°C ambient operating temperature