Renesas Electronics 9DB106BGILFT PLL Clock Buffer 28-Pin TSSOP-28
- N° de stock RS:
- 264-3528
- Référence fabricant:
- 9DB106BGILFT
- Fabricant:
- Renesas Electronics
Sous-total (1 paquet de 2 unités)*
7,85 €
(TVA exclue)
9,498 €
(TVA incluse)
Frais de livraison offerts pour toute commande de plus de 75,00 €
En stock
- Plus 1 920 unité(s) expédiée(s) à partir du 23 février 2026
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Unité | Prix par unité | le paquet* |
|---|---|---|
| 2 + | 3,925 € | 7,85 € |
*Prix donné à titre indicatif
- N° de stock RS:
- 264-3528
- Référence fabricant:
- 9DB106BGILFT
- Fabricant:
- Renesas Electronics
Spécifications
Documentation technique
Législations et de normes
Détails du produit
Recherchez des produits similaires en sélectionnant un ou plusieurs attributs.
Sélectionner tout | Attribut | Valeur |
|---|---|---|
| Marque | Renesas Electronics | |
| Product Type | PLL Clock Buffer | |
| Maximum Input Frequency | 105MHz | |
| Mount Type | Surface | |
| Package Type | TSSOP-28 | |
| Pin Count | 28 | |
| Number of Outputs | 6 | |
| Minimum Supply Voltage | 3.3V | |
| Maximum Supply Voltage | 4.6V | |
| Minimum Operating Temperature | -65°C | |
| Maximum Operating Temperature | 150°C | |
| Height | 1.2mm | |
| Series | 9DB106 | |
| Standards/Approvals | RoHS | |
| Length | 6.4mm | |
| Automotive Standard | No | |
| Sélectionner tout | ||
|---|---|---|
Marque Renesas Electronics | ||
Product Type PLL Clock Buffer | ||
Maximum Input Frequency 105MHz | ||
Mount Type Surface | ||
Package Type TSSOP-28 | ||
Pin Count 28 | ||
Number of Outputs 6 | ||
Minimum Supply Voltage 3.3V | ||
Maximum Supply Voltage 4.6V | ||
Minimum Operating Temperature -65°C | ||
Maximum Operating Temperature 150°C | ||
Height 1.2mm | ||
Series 9DB106 | ||
Standards/Approvals RoHS | ||
Length 6.4mm | ||
Automotive Standard No | ||
- Pays d'origine :
- TW
The Renesas Electronics differential buffer is a zero delay buffer which supports PCIe Gen1 and Gen2 clocking requirements. It is driven by a differential SRC output pair from an IDT CK410 or CK505 compliant main clock generator. It attenuates jitter on the input clock and has a selectable PLL bandwidth to maximize performance in systems with or without spread spectrum clocking. An SMBus interface allows control of the PLL bandwidth and bypass options while 2 clock request pins make the device suitable for express card applications.
SMBus interface or unused outputs can be disabled here
Spread spectrum compatible or tracks spreading input clock for low EMI available
PLL or bypass mode or PLL can dejitter incoming clock present
6 to 0.7 V current mode differential output pairs
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