Silicon Labs Clock Signal Conditioner

The integrated multi-DSPLL technology reduces the PCB footprint and BOM by reducing the need for additional external components. Its 3 DSPLL can simultanously generate any combination of low jitter SyncE and IEEE-1588 compliant synchronization clocks.

The Si5348 easily meets the jitter specifications of 25G, 40G and 100G PHYs, removing the need for additional components.

Simple, intuitive configuration and customisation with Silicon Lab's ClockBuilder Pro software suite.